Invention Grant
- Patent Title: Control of length in gate region during processing of VFET structures
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Application No.: US15662526Application Date: 2017-07-28
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Publication No.: US10461196B2Publication Date: 2019-10-29
- Inventor: Chanro Park , Steven Bentley , Ruilong Xie , Min Gyu Sung
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Anthony Canale
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L21/84 ; H01L27/12 ; H01L29/423 ; H01L29/66 ; H01L29/78

Abstract:
Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
Public/Granted literature
- US20190035938A1 CONTROL OF LENGTH IN GATE REGION DURING PROCESSING OF VFET STRUCTURES Public/Granted day:2019-01-31
Information query
IPC分类: