Invention Grant
- Patent Title: Valid lane training
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Application No.: US15761408Application Date: 2015-09-26
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Publication No.: US10461805B2Publication Date: 2019-10-29
- Inventor: Venkatraman Iyer , Lip Khoon Teh , Mahesh Wagh , Zuoguo Wu , Azydee Hamid , Gerald S. Pasdast
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- International Application: PCT/US2015/052512 WO 20150926
- International Announcement: WO2017/052663 WO 20170330
- Main IPC: H04B3/40
- IPC: H04B3/40 ; G06F13/20 ; H04L25/03

Abstract:
One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.
Public/Granted literature
- US20190238179A1 VALID LANE TRAINING Public/Granted day:2019-08-01
Information query