利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

110 条记录 (耗时 0.042 秒)

    STREAM IDENTIFIER LANE PROTECTION
    2.
    发明申请
    STREAM IDENTIFIER LANE PROTECTION 审中-公开

    公开(公告)号：US20200244397A1

    公开(公告)日：2020-07-30

    申请号：US15761409

    申请日：2015-09-26

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Mahesh Wagh ,  Joon Teik HOR

    IPC分类号： H04L1/00

    摘要： Data of different types are received on a plurality of data lanes of a physical link. Particular data is received on at least a portion of the plurality of data lanes, and a stream signal, corresponding to the particular data, is received on another of the lanes of the physical link, where the particular data is of a particular type different from other data previously sent on the plurality of data lanes. The stream signal includes a code component indicating that the particular data is of the particular type and a parity component for use in identifying whether a bit error is present in the stream signal.

    Valid lane training
    3.
    发明授权
    Valid lane training 有权

    公开(公告)号：US10461805B2

    公开(公告)日：2019-10-29

    申请号：US15761408

    申请日：2015-09-26

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC分类号： H04B3/40 ,  G06F13/20 ,  H04L25/03

    摘要： One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    4.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20190310959A1

    公开(公告)日：2019-10-10

    申请号：US16446996

    申请日：2019-06-20

    申请人： INTEL CORPORATION

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    Bimodal PHY for low latency in high speed interconnects
    6.
    发明授权
    Bimodal PHY for low latency in high speed interconnects 有权

    公开(公告)号：US10372657B2

    公开(公告)日：2019-08-06

    申请号：US15390648

    申请日：2016-12-26

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.

    High performance interconnect link state transitions
    7.
    发明授权
    High performance interconnect link state transitions 有权

    公开(公告)号：US10324882B2

    公开(公告)日：2019-06-18

    申请号：US15393631

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： William R. Halleck ,  Rahul R. Shah ,  Venkatraman Iyer

    IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/12

    摘要： An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION
    8.
    发明申请
    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION 审中-公开

    公开(公告)号：US20180191523A1

    公开(公告)日：2018-07-05

    申请号：US15394278

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： Rahul R. Shah ,  William R. Halleck ,  Fulvio Spagna ,  Venkatraman Iyer

    IPC分类号： H04L12/407 ,  H04L12/933 ,  H04B3/36

    CPC分类号： H04B3/36 ,  G06F13/40 ,  H04L47/125

    摘要： An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing
    9.
    发明授权
    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing 有权

    公开(公告)号：US09817054B2

    公开(公告)日：2017-11-14

    申请号：US13729756

    申请日：2012-12-28

    申请人： Intel Corporation

    发明人： Thanunathan Rangarajan ,  Shreesh Chhabbi ,  Arvind A. Kumar ,  Venkatraman Iyer

    IPC分类号： G01R31/04 ,  G01R31/30

    CPC分类号： G01R31/04 ,  G01R31/30

    摘要： Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.