- Patent Title: Technologies for memory margin aware reliable software execution
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Application No.: US15465210Application Date: 2017-03-21
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Publication No.: US10467028B2Publication Date: 2019-11-05
- Inventor: Krishnaprasad H , Ramkumar Jayaraman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/445 ; G06F9/4401 ; G06F9/48 ; G06F3/06

Abstract:
Technologies for reliable software execution include a computing device having a memory that includes multiple ranks. The computing device trains the ranks of the memory and determines a consolidated memory score for each rank. Each consolidated memory score is indicative of a margin of the corresponding rank. The computing device identifies a higher-margin address range using the consolidated memory scores. The higher-margin memory address range is mapped to a higher-margin memory rank. The computing device loads high-priority software into the higher-margin memory address range. The high-priority software may include an operating system or a critical application. A pre-boot firmware environment may publish the consolidated memory scores to a higher-level software component, such as the operating system. The pre-boot firmware environment may map a predetermined address range to the higher-margin memory rank. A critical application may request to be loaded into a higher-margin address range. Other embodiments are described and claimed.
Public/Granted literature
- US20180276010A1 TECHNOLOGIES FOR MEMORY MARGIN AWARE RELIABLE SOFTWARE EXECUTION Public/Granted day:2018-09-27
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