公开(公告)号：US10811076B1

公开(公告)日：2020-10-20

申请号：US16458023

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Ramkumar Jayaraman ,  Krishnaprasad H ,  Kausik Ghosh

IPC: G11C7/00 ,  G11C11/406 ,  G11C5/04 ,  G06F1/3225 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4093 ,  G06F1/3234

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

公开(公告)号：US11443793B2

公开(公告)日：2022-09-13

申请号：US17068732

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Ramkumar Jayaraman ,  Krishnaprasad H ,  Kausik Ghosh

IPC: G11C11/406 ,  G11C5/04 ,  G11C11/4096 ,  G11C11/4093 ,  G06F1/3225 ,  G11C11/4074 ,  G06F1/3234

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

公开(公告)号：US20220188019A1

公开(公告)日：2022-06-16

申请号：US17688631

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Ramkumar Jayaraman ,  Saravanan Sethuraman ,  Diyanesh Babu Chinnakkonda Vidyapoornachary ,  Krishnaprasad H

IPC: G06F3/06

Abstract: A memory system includes a first set of memory devices, a second set of memory devices, and a memory controller circuit system. The memory controller circuit system groups a first one of the memory devices in each of the first and the second sets into a first virtual memory rank based on eye margins of first data signals sampled by the first virtual memory rank. The memory controller circuit system groups a second one of the memory devices in each of the first and the second sets into a second virtual memory rank based on eye margins of second data signals sampled by the second virtual memory rank. The memory controller circuit system accesses the memory devices in the first virtual memory rank separately from the memory devices in the second virtual memory rank during data access operations.

公开(公告)号：US20220188001A1

公开(公告)日：2022-06-16

申请号：US17689816

申请日：2022-03-08

Applicant: Intel Corporation

Inventor： Ramkumar JAYARAMAN ,  Krishnaprasad H ,  Robert A. BRANCH

IPC: G06F3/06

Abstract: Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and/or applications based on a memory access rate of the VMs/applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs/applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

公开(公告)号：US20210043247A1

公开(公告)日：2021-02-11

申请号：US17068732

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Ramkumar Jayaraman ,  Krishnaprasad H ,  Kausik Ghosh

IPC: G11C11/406 ,  G11C5/04 ,  G06F1/3225 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4093 ,  G06F1/3234

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

公开(公告)号：US10467028B2

公开(公告)日：2019-11-05

申请号：US15465210

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Krishnaprasad H ,  Ramkumar Jayaraman

IPC: G06F9/44 ,  G06F9/445 ,  G06F9/4401 ,  G06F9/48 ,  G06F3/06

Abstract: Technologies for reliable software execution include a computing device having a memory that includes multiple ranks. The computing device trains the ranks of the memory and determines a consolidated memory score for each rank. Each consolidated memory score is indicative of a margin of the corresponding rank. The computing device identifies a higher-margin address range using the consolidated memory scores. The higher-margin memory address range is mapped to a higher-margin memory rank. The computing device loads high-priority software into the higher-margin memory address range. The high-priority software may include an operating system or a critical application. A pre-boot firmware environment may publish the consolidated memory scores to a higher-level software component, such as the operating system. The pre-boot firmware environment may map a predetermined address range to the higher-margin memory rank. A critical application may request to be loaded into a higher-margin address range. Other embodiments are described and claimed.

公开(公告)号：US20180276010A1

公开(公告)日：2018-09-27

申请号：US15465210

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Krishnaprasad H ,  Ramkumar Jayaraman

IPC: G06F9/445 ,  G06F9/44 ,  G06F9/48 ,  G06F3/06

Abstract: Technologies for reliable software execution include a computing device having a memory that includes multiple ranks. The computing device trains the ranks of the memory and determines a consolidated memory score for each rank. Each consolidated memory score is indicative of a margin of the corresponding rank. The computing device identifies a higher-margin address range using the consolidated memory scores. The higher-margin memory address range is mapped to a higher-margin memory rank. The computing device loads high-priority software into the higher-margin memory address range. The high-priority software may include an operating system or a critical application. A pre-boot firmware environment may publish the consolidated memory scores to a higher-level software component, such as the operating system. The pre-boot firmware environment may map a predetermined address range to the higher-margin memory rank. A critical application may request to be loaded into a higher-margin address range. Other embodiments are described and claimed.