Invention Grant
- Patent Title: Method and system for implementing high speed source synchronous clock alignment
-
Application No.: US15714756Application Date: 2017-09-25
-
Publication No.: US10476658B1Publication Date: 2019-11-12
- Inventor: Sathish Kumar Ganesan , Fred Staples Stivers
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: H04L7/033
- IPC: H04L7/033
Abstract:
Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.
Information query
