公开(公告)号：US11238204B1

公开(公告)日：2022-02-01

申请号：US17066284

申请日：2020-10-08

Applicant: Cadence Design Systems, Inc.

Inventor： Scott David Huss ,  Loren B. Reiss ,  Fred Staples Stivers ,  Steven Martin Broome

IPC: G06F30/30 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3187 ,  G06F30/333

Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

公开(公告)号：US11190331B1

公开(公告)日：2021-11-30

申请号：US17124280

申请日：2020-12-16

Applicant: Cadence Design Systems, Inc.

Inventor： Loren B. Reiss ,  Scott David Huss ,  Fred Staples Stivers ,  James Dennis Vandersand, Jr.

IPC: H04L7/00

Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.

公开(公告)号：US10476658B1

公开(公告)日：2019-11-12

申请号：US15714756

申请日：2017-09-25

Applicant: Cadence Design Systems, Inc.

Inventor： Sathish Kumar Ganesan ,  Fred Staples Stivers

IPC: H04L7/033

Abstract: Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.

公开(公告)号：US11108425B1

公开(公告)日：2021-08-31

申请号：US17005092

申请日：2020-08-27

Applicant: Cadence Design Systems, Inc.

Inventor： Scott David Huss ,  Loren B. Reiss ,  Fred Staples Stivers ,  Matthew Robert Collin ,  James Lee House ,  Ramakrishna Kasukurthi

IPC: H04B1/38 ,  H04L5/16 ,  H04B1/401 ,  H04B1/58 ,  H04B1/48

Abstract: A calibration control component within a transmit (TX) or receive (RX) device executes a calibration sequence to ensure reliable data transmission and reception within the device. The calibration sequence comprises a set of calibration functions that are sequentially executed. The calibration control component detects a pause function being enabled based on a pause function configuration register. Based on detecting the pause function being enabled, the calibration control component pauses execution of the calibration sequence.

公开(公告)号：US10992449B1

公开(公告)日：2021-04-27

申请号：US16940343

申请日：2020-07-27

Applicant: Cadence Design Systems, Inc.

Inventor： Loren B. Reiss ,  Fred Staples Stivers ,  Eric Harris Naviasky

IPC: H04K1/10 ,  H04L27/28 ,  H04L7/00 ,  H04L7/02 ,  G06F9/30

Abstract: A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a corresponding serializer. The set of serializers generates serialized data based on the set of balanced bit sequences.

公开(公告)号：US09940288B1

公开(公告)日：2018-04-10

申请号：US14948761

申请日：2015-11-23

Applicant: Cadence Design Systems, Inc.

Inventor： Loren Blair Reiss ,  Fred Staples Stivers ,  Scott Gerald Bare

IPC: G06F13/40 ,  H04L7/04 ,  G06F13/20 ,  H04L7/033

CPC classification number: G06F13/4068 ,  G06F13/20 ,  H04L7/033 ,  H04L7/04

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.