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公开(公告)号：US10476658B1
公开(公告)日：2019-11-12
申请号：US15714756
申请日：2017-09-25
Applicant: Cadence Design Systems, Inc.
Inventor： Sathish Kumar Ganesan , Fred Staples Stivers
IPC: H04L7/033
Abstract: Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.
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