- Patent Title: Read disturb detection based on dynamic bit error rate estimation
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Application No.: US15850273Application Date: 2017-12-21
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Publication No.: US10482983B2Publication Date: 2019-11-19
- Inventor: Abdel Hakim Alhussien , Ludovic Danjean , Sundararajan Sankaranarayanan , Erich Franz Haratsch
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Hall Estill Attorneys at Law
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C16/10 ; G11C16/26 ; G11C11/56 ; G06F11/10 ; G11C7/04

Abstract:
Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.
Public/Granted literature
- US20180182465A1 Read Disturb Detection Based on Dynamic Bit Error Rate Estimation Public/Granted day:2018-06-28
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