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公开(公告)号：US20180287635A1
公开(公告)日：2018-10-04
申请号：US15478895
申请日：2017-04-04
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC: H03M13/11
CPC classification number: H03M13/1111
Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US20180182465A1
公开(公告)日：2018-06-28
申请号：US15850273
申请日：2017-12-21
Applicant: Seagate Technology LLC
Inventor： Abdel Hakim Alhussien , Ludovic Danjean , Sundararajan Sankaranarayanan , Erich Franz Haratsch
Abstract: Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.
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公开(公告)号：US11500547B2
公开(公告)日：2022-11-15
申请号：US17168786
申请日：2021-02-05
Applicant: Seagate Technology, LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Sundararajan Sankaranarayanan , Erich Franz Haratsch
IPC: G06F3/06
Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
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公开(公告)号：US20210181954A1
公开(公告)日：2021-06-17
申请号：US17168786
申请日：2021-02-05
Applicant: Seagate Technology, LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Sundararajan Sankaranarayanan , Erich Franz Haratsch
IPC: G06F3/06
Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
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公开(公告)号：US20200286577A1
公开(公告)日：2020-09-10
申请号：US16883081
申请日：2020-05-26
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Erich Franz Haratsch
Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.
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Patent Agency Ranking
公开(公告)号：US10276247B2
公开(公告)日：2019-04-30
申请号：US15205654
申请日：2016-07-08
Applicant: Seagate Technology LLC
Inventor： AbdelHakim S. Alhussien , Sundararajan Sankaranarayanan , Thuy Van Nguyen , Ludovic Danjean , Erich F. Haratsch
Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
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公开(公告)号：US20210011631A1
公开(公告)日：2021-01-14
申请号：US16505909
申请日：2019-07-09
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Sundararajan Sankaranarayanan , Erich Franz Haratsch
IPC: G06F3/06
Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
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公开(公告)号：US10482983B2
公开(公告)日：2019-11-19
申请号：US15850273
申请日：2017-12-21
Applicant: Seagate Technology LLC
Inventor： Abdel Hakim Alhussien , Ludovic Danjean , Sundararajan Sankaranarayanan , Erich Franz Haratsch
Abstract: Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.
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公开(公告)号：US10276233B1
公开(公告)日：2019-04-30
申请号：US15799484
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.
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公开(公告)号：US10177787B1
公开(公告)日：2019-01-08
申请号：US14856674
申请日：2015-09-17
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.
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