Invention Grant
- Patent Title: Electronic package and fabrication method
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Application No.: US16035083Application Date: 2018-07-13
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Publication No.: US10483181B2Publication Date: 2019-11-19
- Inventor: Karine Saxod , Nicolas Mastromauro
- Applicant: STMicroelectronics (Grenoble 2) SAS
- Applicant Address: FR Grenoble
- Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee Address: FR Grenoble
- Agency: Crowe & Dunlevy
- Priority: FR1756798 20170718
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L23/31 ; H01L23/32 ; H01L23/04 ; H01L23/10

Abstract:
An integrated circuit chip is mounted to a front face of a support plate. An encapsulation cap in then mounted to the support plate. The encapsulation cap includes a front wall and a peripheral wall having an end edge at least partly facing a peripheral zone of the support plate. The support plate and the encapsulation cap delimit a chamber in which the integrated circuit chip is situated. To mount the encapsulation cap, a bead of glue is inserted between the peripheral zone and the end edge of the peripheral wall of the encapsulation cap. A peripheral outer face of the encapsulation cap includes a recess extending from the end edge which locally uncovers a part of the bead of glue. A local hardening of the glue at the recess is performed as a first attachment step. Further hardening of the remainder of the glue is then performed.
Public/Granted literature
- US20190027416A1 ELECTRONIC PACKAGE AND FABRICATION METHOD Public/Granted day:2019-01-24
Information query
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