Invention Grant
- Patent Title: Configuration of multi-die modules with through-silicon vias
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Application No.: US15964647Application Date: 2018-04-27
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Publication No.: US10509752B2Publication Date: 2019-12-17
- Inventor: Russell Schreiber , John Wuu , Michael K. Ciraula , Patrick J. Shyvers
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polansky; Rosalynn M. Smith
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G06F13/38 ; G06F13/42 ; H01L25/065 ; G06F13/40

Abstract:
A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.
Public/Granted literature
- US20190332561A1 CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS Public/Granted day:2019-10-31
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