- 专利标题: Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
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申请号: US15594443申请日: 2017-05-12
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公开(公告)号: US10510703B2公开(公告)日: 2019-12-17
- 发明人: HeeJo Chi , HanGil Shin , NamJu Cho
- 申请人: STATS ChipPAC Pte. Ltd.
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Patent Law Group: Atkins and Associates, P.C.
- 代理商 Brian M. Kaufman; Robert D. Atkins
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/528 ; H01L21/768 ; H01L23/498 ; H01L21/56 ; H01L21/48 ; H01L23/538 ; H01L21/683
摘要:
A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
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