Invention Grant
- Patent Title: Block-level design method for heterogeneous PG-structure cells
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Application No.: US15723308Application Date: 2017-10-03
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Publication No.: US10515175B2Publication Date: 2019-12-24
- Inventor: Yen-Hung Lin , Yuan-Te Hou , Chung-Hsing Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.
Public/Granted literature
- US20180210993A1 BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS Public/Granted day:2018-07-26
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