公开(公告)号：US20190006346A1

公开(公告)日：2019-01-03

申请号：US16125965

申请日：2018-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.

公开(公告)号：US09659141B2

公开(公告)日：2017-05-23

申请号：US14833364

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Cheng-I Huang ,  Chin-Chang Hsu ,  Hung Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

公开(公告)号：US09141752B2

公开(公告)日：2015-09-22

申请号：US14187421

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Cheng-I Huang ,  Chin-Chang Hsu ,  Hung Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract translation: 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。

公开(公告)号：US11176303B2

公开(公告)日：2021-11-16

申请号：US16686711

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F7/50 ,  G06F30/392 ,  G06F111/04

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

公开(公告)号：US10318698B2

公开(公告)日：2019-06-11

申请号：US15595863

申请日：2017-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chin-Chang Hsu

IPC: G06F17/50 ,  G03F1/70

Abstract: A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.

公开(公告)号：US10268791B2

公开(公告)日：2019-04-23

申请号：US14967061

申请日：2015-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Chin-Chou Liu ,  Chi-Wei Hu

IPC: G06F17/50

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.

公开(公告)号：US20180330034A1

公开(公告)日：2018-11-15

申请号：US15878818

申请日：2018-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/06

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

公开(公告)号：US12131109B2

公开(公告)日：2024-10-29

申请号：US18513349

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G06F30/396 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/394 ,  G06F30/396 ,  G06F30/398 ,  G06F2119/06 ,  G06F2119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US11853678B2

公开(公告)日：2023-12-26

申请号：US18096906

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F2119/06 ,  G06F2119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US11182527B2

公开(公告)日：2021-11-23

申请号：US16837449

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F30/392 ,  G06F30/39 ,  G06F30/30 ,  G06F30/347 ,  H01L27/02 ,  H01L29/06 ,  G06F111/20 ,  G06F30/398

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.