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    Integrated circuit with mixed row heights
    1.
    发明授权
    Integrated circuit with mixed row heights 有权

    公开(公告)号：US12230624B2

    公开(公告)日：2025-02-18

    申请号：US18232759

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

    IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

    Integrated circuit with mixed row heights
    3.
    发明授权
    Integrated circuit with mixed row heights 有权

    公开(公告)号：US11769766B2

    公开(公告)日：2023-09-26

    申请号：US17585402

    申请日：2022-01-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

    IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

    CPC classification number: H01L27/0207 ,  H01L27/0924 ,  G06F2111/20

    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

    Power grid, IC and method for placing power grid
    5.
    发明授权
    Power grid, IC and method for placing power grid 有权

    公开(公告)号：US11068638B2

    公开(公告)日：2021-07-20

    申请号：US16875060

    申请日：2020-05-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC: G06F30/392 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/394 ,  G06F119/06

    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.

    Circuit testing and manufacture using multiple timing libraries
    7.
    发明授权
    Circuit testing and manufacture using multiple timing libraries 有权

    公开(公告)号：US10977402B2

    公开(公告)日：2021-04-13

    申请号：US16676210

    申请日：2019-11-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ravi Babu Pittu ,  Chung-Hsing Wang ,  Sung-Yen Yeh ,  Li Chung Hsu

    IPC: G06F17/50 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/367 ,  G06F119/12

    Abstract: A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

    CONSTRAINED CELL PLACEMENT
    8.
    发明申请
    CONSTRAINED CELL PLACEMENT 审中-公开

    公开(公告)号：US20200082046A1

    公开(公告)日：2020-03-12

    申请号：US16686711

    申请日：2019-11-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

    IPC: G06F17/50

    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

    TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERCONNECT
    9.
    发明申请
    TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERCONNECT 审中-公开

    公开(公告)号：US20190108304A1

    公开(公告)日：2019-04-11

    申请号：US16205441

    申请日：2018-11-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

    IPC: G06F17/50 ,  H03K5/15 ,  H01L23/528

    Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

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