Invention Grant
- Patent Title: Wobble reduction in an integer mode digital phase locked loop
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Application No.: US16214179Application Date: 2018-12-10
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Publication No.: US10516401B2Publication Date: 2019-12-24
- Inventor: Jayawardan Janardhanan , Eric Paul Lindgren , Henry Yao
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H03L7/081
- IPC: H03L7/081 ; H03L7/10

Abstract:
A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.
Public/Granted literature
- US20190280649A1 WOBBLE REDUCTION IN AN INTEGER MODE DIGITAL PHASE LOCKED LOOP Public/Granted day:2019-09-12
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