Invention Grant
- Patent Title: Current sink with negative voltage tolerance
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Application No.: US15832071Application Date: 2017-12-05
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Publication No.: US10520971B2Publication Date: 2019-12-31
- Inventor: Sri Navaneethakrishnan Easwaran , Vijayalakshmi Devarajan , Timothy Paul Duryea , Shanmuganand Chellamuthu
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Ciminio
- Main IPC: G05F3/26
- IPC: G05F3/26 ; B60T8/172 ; B60T8/1761 ; H03K17/687

Abstract:
A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
Public/Granted literature
- US20190025866A1 CURRENT SINK WITH NEGATIVE VOLTAGE TOLERANCE Public/Granted day:2019-01-24
Information query
IPC分类: