Invention Grant
- Patent Title: Semiconductor package and semiconductor process
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Application No.: US15614563Application Date: 2017-06-05
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Publication No.: US10522492B2Publication Date: 2019-12-31
- Inventor: Wen Hung Huang , Yan Wen Chung , Chien-Mei Huang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/522 ; H01L21/768 ; H01L23/14 ; H01L23/04 ; H01L23/498 ; H01L21/3213

Abstract:
A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.
Public/Granted literature
- US20180350616A1 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS Public/Granted day:2018-12-06
Information query
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