公开(公告)号：US11887943B2

公开(公告)日：2024-01-30

申请号：US17684375

申请日：2022-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19103

Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.

公开(公告)号：US11328989B2

公开(公告)日：2022-05-10

申请号：US16821838

申请日：2020-03-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L25/075

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer. A line width of the circuit layer of the redistribution layer is less than a line width of the circuit layer of the upper conductive structure and a line width of the circuit layer of the lower conductive structure.

公开(公告)号：US11139232B2

公开(公告)日：2021-10-05

申请号：US16812235

申请日：2020-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A wiring structure and a method for manufacturing a wiring structure are provided. The wiring structure includes a first conductive structure, a second conductive structure, a dent structure and an adhesion layer. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The dent structure is attached to the first conductive structure. The adhesion layer is interposed between the first conductive structure and the second conductive structure to bond the first conductive structure and the second conductive structure together. A periphery portion of the adhesion layer is disposed in a gap between the dent structure and the second conductive structure.

公开(公告)号：US10756054B1

公开(公告)日：2020-08-25

申请号：US16521526

申请日：2019-07-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a core layer having a first surface and a second surface opposite to the first surface. The core layer includes a cavity. A first die is in the cavity. A first gap is between a sidewall of the cavity and a sidewall of the first die. A filling material is in the first gap. The filling material includes a first dimple in proximal to the second surface of the core layer. A first buffer layer on the second surface of the core layer. The first buffer layer has a bottom surface in proximal to the first die and a top surface opposite to the bottom surface. The first buffer layer filling the first dimple. A method for manufacturing a semiconductor package is also disclosed.

公开(公告)号：US11488901B2

公开(公告)日：2022-11-01

申请号：US16862453

申请日：2020-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L21/48

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

公开(公告)号：US11410944B2

公开(公告)日：2022-08-09

申请号：US16557993

申请日：2019-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/31 ,  H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01Q1/38 ,  H01L23/00

Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.

公开(公告)号：US11355426B2

公开(公告)日：2022-06-07

申请号：US16945429

申请日：2020-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Min Lung Huang

IPC: H05K1/02 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K1/18

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.

公开(公告)号：US11329007B2

公开(公告)日：2022-05-10

申请号：US16996872

申请日：2020-08-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Huei-Shyong Cho

IPC: H05K1/11 ,  H05K3/42 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/66 ,  H01L21/683 ,  H01L23/66 ,  H01L25/16

Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.

公开(公告)号：US11309264B2

公开(公告)日：2022-04-19

申请号：US16833330

申请日：2020-03-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

公开(公告)号：US11302619B2

公开(公告)日：2022-04-12

申请号：US16590173

申请日：2019-10-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H05K1/18 ,  H05K1/16

Abstract: A device structure includes a stacked structure, a dielectric material, and an electrode via. The stacked structure includes a first metal oxide layer, a second metal oxide layer and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is interposed between the first metal oxide layer and the second metal oxide layer. The dielectric material extends through the first metal oxide layer. The electrode via extends through the dielectric material and electrically connected to the metal layer.