Invention Grant
- Patent Title: Via blocking layer
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Application No.: US16302692Application Date: 2016-06-22
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Publication No.: US10535601B2Publication Date: 2020-01-14
- Inventor: Rami Hourani , Marie Krysak , Florian Gstrein , Ruth A. Brain , Mark T. Bohr , Manish Chandhok
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2016/038686 WO 20160622
- International Announcement: WO2017/222515 WO 20171228
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L21/02 ; H01L21/762 ; H01L21/8234

Abstract:
An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.
Public/Granted literature
- US20190122982A1 VIA BLOCKING LAYER Public/Granted day:2019-04-25
Information query
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