公开(公告)号：US20240360264A1

公开(公告)日：2024-10-31

申请号：US18766426

申请日：2024-07-08

申请人： Intel Corporation

发明人： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

摘要： A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

摘要： DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.

公开(公告)号：US11532724B2

公开(公告)日：2022-12-20

申请号：US17154755

申请日：2021-01-21

申请人： Intel Corporation

发明人： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US11315798B2

公开(公告)日：2022-04-26

申请号：US16075555

申请日：2016-04-08

申请人： Intel Corporation

发明人： Robert L. Bristol ,  Marie Krysak ,  James M. Blackwell ,  Florian Gstrein ,  Kent N. Frasure

IPC分类号： G03F7/039 ,  H01L21/311 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

摘要： Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US10756215B2

公开(公告)日：2020-08-25

申请号：US16271226

申请日：2019-02-08

申请人： Intel Corporation

发明人： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/31 ,  H01L23/498 ,  H01L21/32 ,  H01L29/423

摘要： Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20190189505A1

公开(公告)日：2019-06-20

申请号：US16326135

申请日：2016-09-29

申请人： INTEL CORPORATION

发明人： Scott B. Clendenning ,  Florian Gstrein

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L23/53295

摘要： Disclosed are electronic device assemblies, computing devices, and related methods. An electronic device assembly or a computing device includes an interlayer dielectric region between a first region and a second region, a conductive interlayer structure formed through the interlayer dielectric region, and a barrier region formed around the conductive interlayer structure. The conductive interlayer structure includes a composition of Ml-Alm—X1n—X2p—Cq—Or, wherein M comprises a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium; C comprises carbon; O comprises oxygen; X1 comprises gallium; X2 comprises indium; and l, m, n, p, q and r represent an atomic percent of an element in the barrier region that can be 0 percent, but n and p cannot both be 0 percent. A method includes forming the barrier region within a passage through the interlayer dielectric region.

公开(公告)号：US20190122982A1

公开(公告)日：2019-04-25

申请号：US16302692

申请日：2016-06-22

申请人： Intel Corporation

发明人： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr ,  Manish Chandhok

IPC分类号： H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L23/5226 ,  H01L21/02172 ,  H01L21/76224 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/823475 ,  H01L23/528 ,  H01L2221/1063

摘要： An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.

公开(公告)号：US09899255B2

公开(公告)日：2018-02-20

申请号：US15528427

申请日：2014-12-23

申请人： INTEL CORPORATION

发明人： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

摘要： Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US12087594B2

公开(公告)日：2024-09-10

申请号：US17124730

申请日：2020-12-17

申请人： INTEL CORPORATION

发明人： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831

摘要： Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US20240222119A1

公开(公告)日：2024-07-04

申请号：US18147107

申请日：2022-12-28

申请人： Intel Corporation

发明人： Eungnak Han ,  James Blackwell ,  Gurpreet Singh ,  Florian Gstrein

IPC分类号： H01L21/027 ,  H01L21/02

CPC分类号： H01L21/0274 ,  H01L21/02118 ,  H01L21/02345 ,  C08F293/00

摘要： In-situ formation of a block copolymer through deprotection can provide patterns with flexible pitches. A layer of a protected polymer including a protecting group is formed. One or more portions of the layer may be exposed to light. The exposed portion(s) may be baked after the light exposure. The protecting group is removed after the light exposure or bake so that the protected polymer becomes a deprotected polymer in the exposure portion(s). The deprotected polymer is bonded with the protected polymer in the unexposed portion(s) of the layer but has a different solubility from the protected polymer so that phases of the block copolymer are separated. The phase separation can provide a periodic pattern with various pitches. The solution and roughness of the pattern can be enhanced by using CARs formed with a protected, cross-linked polymer that includes a protective group and a function group with a ratio of 50:50.