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    Conductive via and metal line end fabrication and structures resulting therefrom
    1.
    发明授权
    Conductive via and metal line end fabrication and structures resulting therefrom 有权

    公开(公告)号：US11145541B2

    公开(公告)日：2021-10-12

    申请号：US16637930

    申请日：2017-09-30

    申请人： Intel Corporation

    发明人： Charles H. Wallace ,  Reken Patel ,  Hyunsoo Park ,  Mohit K. Haran ,  Debashish Basu ,  Curtis W. Ward ,  Ruth A. Brain

    IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522

    摘要： Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

    Decoupled via fill
    2.
    发明授权
    Decoupled via fill 有权

    公开(公告)号：US10026649B2

    公开(公告)日：2018-07-17

    申请号：US15528425

    申请日：2014-12-23

    申请人： INTEL CORPORATION

    发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/31 ,  H01L23/528

    摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

    AVD HARDMASK FOR DAMASCENE PATTERNING
    3.
    发明申请
    AVD HARDMASK FOR DAMASCENE PATTERNING 有权

    公开(公告)号：US20170040263A1

    公开(公告)日：2017-02-09

    申请号：US15332199

    申请日：2016-10-24

    申请人： Intel Corporation

    发明人： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

    IPC分类号： H01L23/532 ,  H01L23/528 ,  H01L23/522

    CPC分类号： H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

    摘要翻译： 一种包括在集成电路结构的接触点上形成介电层的方法; 在所述电介质层的表面上形成包括电介质材料的硬掩模; 以及使用所述硬掩模作为图案在所述电介质层中形成至少一个通孔到所述接触点。 一种包括电路基板的装置，包括至少一个包括接触点的活性层; 所述至少一个有源层上的介电层; 包括其中具有用于互连材料的至少一个开口的电介质材料的硬掩模; 以及在硬掩模的至少一个开口中并通过介电层到接触点的互连材料。

    Decoupled via fill
    4.
    发明授权
    Decoupled via fill 有权

    公开(公告)号：US10468298B2

    公开(公告)日：2019-11-05

    申请号：US16249593

    申请日：2019-01-16

    申请人： Intel Corporation

    发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/532 ,  H01L23/528

    摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

    Decoupled via fill
    6.
    发明授权
    Decoupled via fill 有权

    公开(公告)号：US10211098B2

    公开(公告)日：2019-02-19

    申请号：US16005175

    申请日：2018-06-11

    申请人： INTEL CORPORATION

    发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/532

    摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

    LANDING STRUCTURE FOR THROUGH-SILICON VIA
    9.
    发明申请
    LANDING STRUCTURE FOR THROUGH-SILICON VIA 审中-公开
    通过硅的接地结构

    公开(公告)号：US20150137368A1

    公开(公告)日：2015-05-21

    申请号：US14563926

    申请日：2014-12-08

    申请人： Intel Corporation

    发明人： Christopher M. Pelto ,  Ruth A. Brain ,  Kevin J. Lee ,  Gerald S. Leatherman

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5226 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。 在一个实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层 在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。 可以描述和/或要求保护其他实施例。

    Plug and trench architectures for integrated circuits and methods of manufacture
    10.
    发明授权
    Plug and trench architectures for integrated circuits and methods of manufacture 有权

    公开(公告)号：US11171043B2

    公开(公告)日：2021-11-09

    申请号：US16329172

    申请日：2016-09-30

    申请人： Intel Corporation

    发明人： Charles H. Wallace ,  Marvin Y. Paik ,  Hyunsoo Park ,  Mohit K. Haran ,  Alexander F. Kaplan ,  Ruth A. Brain

    IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

    摘要： Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.