Invention Grant
- Patent Title: Forming interconnects with self-assembled monolayers
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Application No.: US15773158Application Date: 2015-12-04
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Publication No.: US10553477B2Publication Date: 2020-02-04
- Inventor: Aranzazu Maestre Caro , Ramanan V. Chebiam
- Applicant: Aranzazu Maestre Caro , Ramanan V. Chebiam , Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- International Application: PCT/US2015/063875 WO 20151204
- International Announcement: WO2017/095432 WO 20170608
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/324 ; C23C18/16 ; B82Y30/00 ; B82Y40/00

Abstract:
Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.
Public/Granted literature
- US20180323101A1 FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS Public/Granted day:2018-11-08
Information query
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