Invention Grant
- Patent Title: Integrated fan-out package and manufacturing method thereof
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Application No.: US15965978Application Date: 2018-04-30
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Publication No.: US10553533B2Publication Date: 2020-02-04
- Inventor: Chun-Lin Lu , Han-Ping Pu , Kai-Chiang Wu , Nan-Chin Chuang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/498 ; H01L23/528 ; H01L23/00

Abstract:
An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
Public/Granted literature
- US20190139890A1 INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-05-09
Information query
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