Invention Grant
- Patent Title: Periphery fill and localized capacitance
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Application No.: US16189416Application Date: 2018-11-13
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Publication No.: US10559339B2Publication Date: 2020-02-11
- Inventor: Christopher John Kawamura , Scott James Derner
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C5/10
- IPC: G11C5/10 ; G11C11/22 ; G11C11/4074 ; H01L27/108 ; H01L27/11507 ; H01L23/528 ; G11C11/408 ; G11C7/08 ; G11C7/12 ; G11C11/4091 ; G11C11/4094 ; G11C5/06

Abstract:
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
Public/Granted literature
- US20190172515A1 PERIPHERY FILL AND LOCALIZED CAPACITANCE Public/Granted day:2019-06-06
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