- Patent Title: Vertical field effect transistor with reduced external resistance
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Application No.: US16007263Application Date: 2018-06-13
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Publication No.: US10559685B2Publication Date: 2020-02-11
- Inventor: Juntao Li , Kangguo Cheng , Choonghyun Lee , Peng Xu
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Thomas S. Grzesik
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/78 ; H01L27/088 ; H01L29/66 ; H01L29/08 ; H01L29/45 ; H01L21/768 ; H01L21/8234 ; H01L27/12 ; H01L21/8238 ; H01L21/84 ; H01L27/092

Abstract:
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer.
Public/Granted literature
- US20190386135A1 VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED EXTERNAL RESISTANCE Public/Granted day:2019-12-19
Information query
IPC分类: