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公开(公告)号：US12094949B2
公开(公告)日：2024-09-17
申请号：US17484019
申请日：2021-09-24
发明人： Choonghyun Lee , Chanro Park , Ruilong Xie , Kangguo Cheng
IPC分类号： H01L29/423 , H01L21/02 , H01L21/28 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/0259 , H01L21/28229 , H01L29/0665 , H01L29/66553 , H01L29/66742 , H01L29/78618 , H01L29/78696 , H01L2029/42388
摘要： Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.
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公开(公告)号：US11842998B2
公开(公告)日：2023-12-12
申请号：US16731210
申请日：2019-12-31
IPC分类号： H01L27/092 , H01L29/165 , H01L29/161 , H01L21/8238 , H01L21/02 , H01L21/324 , H01L29/10 , H01L29/78 , H01L29/66
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823885 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.
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公开(公告)号：US11515217B2
公开(公告)日：2022-11-29
申请号：US17166692
申请日：2021-02-03
发明人： Takashi Ando , Choonghyun Lee , Pouya Hashemi , Jingyun Zhang
IPC分类号： H01L27/082 , H01L21/8238 , H01L29/51 , H01L21/28 , H01L29/08 , H01L27/092 , H01L29/78 , H01L29/10 , H01L29/49
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
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4.发明授权公开(公告)号：US11424343B2
公开(公告)日：2022-08-23
申请号：US16752263
申请日：2020-01-24
发明人： Kangguo Cheng , Juntao Li , Choonghyun Lee , Shogo Mochizuki
摘要： A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.
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公开(公告)号：US11322588B2
公开(公告)日：2022-05-03
申请号：US16601535
申请日：2019-10-14
IPC分类号： H01L29/08 , H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/8238
摘要： A nonplanar MOSFET device such as a FinFET or a sacked nanosheets/nanowires FET has a substrate, one or more nonplanar channels disposed on the substrate, and a gate stack enclosing the nonplanar channels. A first source/drain (S/D) region is disposed on the substrate on a source side of the nonplanar channel and second S/D region is disposed on the substrate on a drain side of the nonplanar channel. The first and second S/D regions made of silicon-germanium (SiGe). In some embodiments, both S/D regions are p-type doped. Contact trenches provide a metallic electrical connection to the first and the second source/drain (S/D) regions. The S/D regions have two parts, a first part with a first concentration of germanium (Ge) and a second part with a second, higher Ge concentration that is a surface layer having convex shape and aligned with one of the contact trenches.
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公开(公告)号：US20220123144A1
公开(公告)日：2022-04-21
申请号：US17566875
申请日：2021-12-31
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/06 , H01L29/786 , H01L29/423
摘要： Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.
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公开(公告)号：US20220093473A1
公开(公告)日：2022-03-24
申请号：US17539669
申请日：2021-12-01
发明人： Choonghyun Lee , Pouya Hashemi , Takashi Ando
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/225 , H01L29/78 , H01L29/66 , H01L27/092 , H01L29/10 , H01L29/165 , H01L29/04 , H01L21/324
摘要： A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.
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8.发明授权公开(公告)号：US11251094B2
公开(公告)日：2022-02-15
申请号：US16784365
申请日：2020-02-07
IPC分类号： H01L21/8238 , H01L27/092
摘要： Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.
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9.发明申请公开(公告)号：US20210375389A1
公开(公告)日：2021-12-02
申请号：US16885317
申请日：2020-05-28
摘要： Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.
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公开(公告)号：US11158715B2
公开(公告)日：2021-10-26
申请号：US16447614
申请日：2019-06-20
IPC分类号： H01L29/76 , H01L29/423 , H01L29/10 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/06 , H01L29/786
摘要： An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.
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