Invention Grant
- Patent Title: Digital phase locked loop for low jitter applications
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Application No.: US16152678Application Date: 2018-10-05
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Publication No.: US10566981B2Publication Date: 2020-02-18
- Inventor: Jingdong Deng , Rupert Shiu Chung Ho , David Flye , Zhenrong Jin , Ramana M. Malladi
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Alvin Borromeo; Andrew M. Calderon
- Main IPC: H03L7/087
- IPC: H03L7/087 ; H03L7/099 ; G06F17/50

Abstract:
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
Public/Granted literature
- US20190036534A1 DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS Public/Granted day:2019-01-31
Information query
IPC分类: