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    Digital phase locked loop for low jitter applications
    2.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10958276B2

    公开(公告)日：2021-03-23

    申请号：US16733669

    申请日：2020-01-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    3.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10566981B2

    公开(公告)日：2020-02-18

    申请号：US16152678

    申请日：2018-10-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    4.
    发明授权
    Digital phase locked loop for low jitter applications 有权
    用于低抖动应用的数字锁相环

    公开(公告)号：US09455728B2

    公开(公告)日：2016-09-27

    申请号：US14245374

    申请日：2014-04-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/087 ,  G06F17/50

    CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Abstract translation: 公开了一种锁相环电路。 锁相环电路包括环形振荡器。 锁相环电路还包括包括数字相位检测器的数字路径。 锁相环电路还包括包括线性相位检测器的模拟路径。 此外，锁相环电路包括将环形振荡器的输出连接到数字路径的输入和模拟路径的输入的反馈路径。 数字路径和模拟路径是并行路径。 数字通道提供数字调谐信号，环形振荡器数字控制环形振荡器的频率。 模拟通道提供模拟调谐信号，环形振荡器可以连续控制环形振荡器的频率。

    Digital phase locked loop for low jitter applications
    5.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10164647B2

    公开(公告)日：2018-12-25

    申请号：US15789035

    申请日：2017-10-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    6.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10103739B2

    公开(公告)日：2018-10-16

    申请号：US15698802

    申请日：2017-09-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    9.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10693471B2

    公开(公告)日：2020-06-23

    申请号：US16030970

    申请日：2018-07-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    10.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10686452B2

    公开(公告)日：2020-06-16

    申请号：US16013236

    申请日：2018-06-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

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