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    Digital phase locked loop for low jitter applications
    1.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10164647B2

    公开(公告)日：2018-12-25

    申请号：US15789035

    申请日：2017-10-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    2.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10103739B2

    公开(公告)日：2018-10-16

    申请号：US15698802

    申请日：2017-09-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Controlled resonant power transfer
    5.
    发明授权
    Controlled resonant power transfer 有权
    控制谐振功率传输

    公开(公告)号：US08791726B2

    公开(公告)日：2014-07-29

    申请号：US13733494

    申请日：2013-01-03

    Applicant: International Business Machines Corporation

    Inventor： Anthony R. Bonaccio ,  Jingdong Deng ,  Zhenrong Jin

    IPC: H03K3/00

    CPC classification number: G06F1/32 ,  G06F1/10

    Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.

    Abstract translation: 提供了时钟分配网络中的回收能量。 电路包括与时钟信号相关联并具有连接到第一负载电容的输出的时钟驱动器。 电路还包括与第一负载电容并联连接的第二负载电容。 电路还包括功率传输电路，其包括串联连接在第一负载电容和第二负载电容之间的电感器和传输栅极。 功率传输电路基于时钟信号控制第一负载电容和第二负载电容之间的能量流动。

    Digital phase locked loop for low jitter applications
    6.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10958276B2

    公开(公告)日：2021-03-23

    申请号：US16733669

    申请日：2020-01-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    BURST NOISE IN LINE TEST
    7.
    发明申请
    BURST NOISE IN LINE TEST 审中-公开
    爆发噪音在线测试

    公开(公告)号：US20140253169A1

    公开(公告)日：2014-09-11

    申请号：US13788125

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kai D. Feng ,  Zhenrong Jin

    IPC: G01R31/26

    CPC classification number: G01R31/2616

    Abstract: A type of device (which can be deployed in a semiconductor manufacturing line) determining whether a device-under-test is generating burst noise. A transimpedance amplifier converts a current-based noise signal to a voltage based noise signal to apply the following tests aimed at determining the presence of burst noise: (i) sufficiently wide pulse width in the noise signal; (ii) sufficiently random pulse width in the noise signal; (iii) sufficiently wide pulse separation in the noise signal; (iv) sufficiently random pulse separation in the noise signal; and (v) sufficiently large pulse amplitude (or magnitude) in the noise signal.

    Abstract translation: 确定被测器件是否产生突发噪声的一种器件（可以部署在半导体生产线中）。 跨阻放大器将基于电流的噪声信号转换为基于电压的噪声信号，以应用以下用于确定突发噪声的存在的测试：（i）噪声信号中足够宽的脉冲宽度; （ii）噪声信号中足够随机的脉冲宽度; （iii）噪声信号中足够宽的脉冲间隔; （iv）噪声信号中足够随机的脉冲分离; 和（v）噪声信号中足够大的脉冲振幅（或幅度）。

    High frequency quadrature PLL circuit and method
    8.
    发明授权
    High frequency quadrature PLL circuit and method 有权
    高频正交PLL电路及方法

    公开(公告)号：US08581648B2

    公开(公告)日：2013-11-12

    申请号：US13761358

    申请日：2013-02-07

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

    IPC: H03L7/06

    CPC classification number: H03L7/08 ,  H03L7/22

    Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

    Abstract translation: 一种方法包括通过向PLL电路的电荷泵的输出施加注入电流来相移锁相环（PLL）电路的输出信号。 电路包括：第一锁相环（PLL）电路和参考相同时钟的第二PLL电路; 相位检测器电路，检测第一PLL电路的输出信号和第二PLL电路的输出信号之间的相位差; 以及可调电流源，其基于相位检测器电路的输出将注入电流施加到第一PLL电路和第二PLL电路中的至少一个。

    Digital phase locked loop for low jitter applications
    9.
    发明授权
    Digital phase locked loop for low jitter applications 有权

    公开(公告)号：US10566981B2

    公开(公告)日：2020-02-18

    申请号：US16152678

    申请日：2018-10-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/087 ,  H03L7/099 ,  G06F17/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Digital phase locked loop for low jitter applications
    10.
    发明授权
    Digital phase locked loop for low jitter applications 有权
    用于低抖动应用的数字锁相环

    公开(公告)号：US09455728B2

    公开(公告)日：2016-09-27

    申请号：US14245374

    申请日：2014-04-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/087 ,  G06F17/50

    CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

    Abstract translation: 公开了一种锁相环电路。 锁相环电路包括环形振荡器。 锁相环电路还包括包括数字相位检测器的数字路径。 锁相环电路还包括包括线性相位检测器的模拟路径。 此外，锁相环电路包括将环形振荡器的输出连接到数字路径的输入和模拟路径的输入的反馈路径。 数字路径和模拟路径是并行路径。 数字通道提供数字调谐信号，环形振荡器数字控制环形振荡器的频率。 模拟通道提供模拟调谐信号，环形振荡器可以连续控制环形振荡器的频率。

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