Invention Grant
- Patent Title: Packet scheduling in a switch for reducing cache-miss rate at a destination network node
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Application No.: US15832806Application Date: 2017-12-06
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Publication No.: US10581762B2Publication Date: 2020-03-03
- Inventor: Alex Shpiner , Tal Anker , Matty Kadosh
- Applicant: Mellanox Technologies TLV Ltd.
- Applicant Address: IL Raanana
- Assignee: MELLANOX TECHNOLOGIES TLV LTD.
- Current Assignee: MELLANOX TECHNOLOGIES TLV LTD.
- Current Assignee Address: IL Raanana
- Agency: Kligler & Associates Patent Attorneys Ltd
- Main IPC: G06F15/16
- IPC: G06F15/16 ; H04L12/861 ; G06F15/173 ; H04L12/863 ; H04L29/08

Abstract:
A network switch includes switch circuitry and multiple ports. The ports are configured to communicate with a communication network. The switch circuitry is configured to receive via the ports multiple packets, which are destined to a destination network node and which specify attributes used by the destination network node as cache keys for on-demand fetching of context items into a cache memory of the destination network node, to control a rate of fetching the context items into the cache memory at the destination network node, by ordering the received packets in a sequence, based on the attributes of the respective packets, using an ordering criterion that aims to place packets that access a common context item in proximity to one another in the sequence, and to forward the received packets to the destination network node, via the ports, in accordance with the ordered sequence.
Public/Granted literature
- US20190173810A1 Packet scheduling in a switch for reducing cache-miss rate at a destination network node Public/Granted day:2019-06-06
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