-
公开(公告)号：US12132656B2
公开(公告)日：2024-10-29
申请号：US16945886
申请日：2020-08-02
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Barak Gafni , Aviv Kfir , Matty Kadosh
Abstract: A method for filtering packets, the method including receiving a plurality of packets, each packet of the plurality of packets including a source address, and for each one packet of the plurality of packets, processing the one packet by performing the following: modifying the source address of the one packet to include at least an identifier of a flow to which the one packet belongs. Related apparatus and methods are also provided.
-
2.发明申请公开(公告)号：US20200169510A1
公开(公告)日：2020-05-28
申请号：US16199288
申请日：2018-11-26
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Matty Kadosh , Aviv Kfir , Jacob Ruthstein , Liron Mula
IPC: H04L12/891 , H04L12/813 , H04L12/819
Abstract: A network element connects over a network to a network node via a member link of a Multi-Chassis—Link Aggregation Link Group (MC-LAG), and further connects, using inter-peer ports, to peer network elements coupled to the network node via other MC-LAG member links. A processor of the network element is configured to receive from the network first packets destined to the network node, to receive via the inter-peer ports information indicative of second packets received from the network by the peer network elements that are destined to the network node, to select at least some of the first packets for transmission at an egress rate that jointly with egress rates of the peer network elements does not exceed a predefined MC-LAG maximal rate, based on the first packets and the information, and to transmit the selected first packets to the network node at the egress rate.
-
公开(公告)号：US20190007301A1
公开(公告)日：2019-01-03
申请号：US15635244
申请日：2017-06-28
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Matty Kadosh , Gil Levy , Aviv Kfir
IPC: H04L12/709 , H04L12/753 , H04L12/741
Abstract: A stacked switch packet communication system is connected to a Multi-Chassis Link Aggregation Group (MLAG). Devices in the system include a designated device for receiving packets that are destined for the MLAG. A new MLAG device is enabled while continuing packet communication by identifying an address of a single port in the new MLAG device. In first updates of the devices the single port is established in the forwarding databases of the devices and the packets transmitted through the devices to the single port. Thereafter, in second updates the single port is replaced in the forwarding databases by another port of the new MLAG device. Upon completion of respective second updates, the packets are transmitted through the devices to the other port in the MLAG.
-
公开(公告)号：US11327974B2
公开(公告)日：2022-05-10
申请号：US16052646
申请日：2018-08-02
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Gil Levy , Aviv Kfir , Salvatore Pontarelli , Pedro Reviriego , Matty Kadosh
IPC: G06F16/2455 , G06F16/28
Abstract: A collection of rules comprising fields that may have wildcard values. The method includes defining first and second subsets of the fields, the second subset being exclusive of the first subset. Intersections of overlapping fields of the first subset are added to the first subset to form an augmented first subset. Metadata from the augmented first subset and the fields not selected for the first subset are combined to define second parts of the rules. Data items are classified by matching a search key to one of the first parts and one of the second parts of the rules.
-
公开(公告)号：US10250489B2
公开(公告)日：2019-04-02
申请号：US15635244
申请日：2017-06-28
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Matty Kadosh , Gil Levy , Aviv Kfir
IPC: H04L12/709 , H04L12/753 , H04L12/741 , H04L12/775 , H04L12/721
Abstract: A stacked switch packet communication system is connected to a Multi-Chassis Link Aggregation Group (MLAG). Devices in the system include a designated device for receiving packets that are destined for the MLAG. A new MLAG device is enabled while continuing packet communication by identifying an address of a single port in the new MLAG device. In first updates of the devices the single port is established in the forwarding databases of the devices and the packets transmitted through the devices to the single port. Thereafter, in second updates the single port is replaced in the forwarding databases by another port of the new MLAG device. Upon completion of respective second updates, the packets are transmitted through the devices to the other port in the MLAG.
-
Patent Agency Ranking
公开(公告)号：US20180019947A1
公开(公告)日：2018-01-18
申请号：US15626135
申请日：2017-06-18
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Alexander Shpiner , Eitan Zahavi , Vladimir Zdornov , Tal Anker , Matty Kadosh
IPC: H04L12/801 , H04L12/707 , H04L12/863 , H04L12/873
CPC classification number: H04L47/10 , H04L45/18 , H04L45/22 , H04L45/28 , H04L47/39 , H04L47/524 , H04L47/627
Abstract: A credit loop that produces a deadlock is identified in a network of switches that are interconnected for packet traffic flows therethrough. The identification is carried out by periodically transmitting respective credit loop control messages from the loop-participating switches via their deadlock-suspected egress ports to respective next-hop switches. The CLCMs has switch port-unique identifiers (SPUIDs). The loop is identified when in one of the next-hop switches the SPUID of a received CLCM is equal to the SPUID of a transmitted CLCM thereof. A master switch is selected for resolving the deadlock.
-
公开(公告)号：US20220294717A1
公开(公告)日：2022-09-15
申请号：US17198298
申请日：2021-03-11
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Alan Lo , Matty Kadosh , Marian Pritsak , Yonatan Piasetsky
Abstract: In one embodiment, a system includes a first data communication device including packet processing circuitry to provide a probe packet including an egress timestamp TS1 indicating a time at which the probe packet egresses the first data communication device, and a network interface to send the probe packet via at least one network connection to a second data communication device, and receive from the second data communication device a response packet including the egress timestamp TS1, wherein the packet processing circuitry is configured to associate with the response packet an ingress timestamp TS2 indicating a time at which the response packet ingresses the first data communication device, and a network metric processor to compute a data latency in the at least one network connection responsively to TS1, TS2, and an indication of an internal latency of the probe packet in the second data communication device.
-
公开(公告)号：US11411911B2
公开(公告)日：2022-08-09
申请号：US17079543
申请日：2020-10-26
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , Vladimir Koushnir , Matty Kadosh , Gil Bloch , Aviad Levy , Liran Liss , Dvir Libhaber
IPC: H04L61/103 , H04L45/02
Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.
-
公开(公告)号：US20210042251A1
公开(公告)日：2021-02-11
申请号：US16537576
申请日：2019-08-11
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Lion Levi , Aviv Kfir , Idan Matari , Ran Shani , Zachy Haramaty , Nir Monovich , Matty Kadosh
IPC: G06F13/28 , G06F13/40 , H04L12/861 , H04L12/725
Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.
-
公开(公告)号：US20190097929A1
公开(公告)日：2019-03-28
申请号：US15713776
申请日：2017-09-25
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Barak Gafni , Matty Kadosh , Aviv Kfir
IPC: H04L12/743 , H04L12/46 , H04L12/713 , H04L12/741
CPC classification number: H04L45/7453 , H04L12/4645 , H04L45/54 , H04L45/586
Abstract: Communication apparatus includes a plurality of interfaces and routing logic coupled between the interfaces. The routing logic includes a parser, which extracts header data from selected fields of each data packet received from the network through an ingress interface. At least one hash calculator computes a hash over a first set of the header data extracted by the parser from each received data packet. A virtual routing and forwarding (VRF) instance selector selects a VRF instance for each received data packet responsively to both an ingress indicator associated with the received data packet and a second set of the header data extracted by the parser from the received data packet. A lookup engine selects an egress interface responsively to the selected VRF instance and the computed hash. Forwarding and switching logic forwards the data packet to the selected egress interface for transmission to the network.
-
-
-
-
-
-
-
-
-
Search Results
27
records
(took 0.013 seconds)
