- 专利标题： Fine-grained analog memory device based on charge-trapping in high-K gate dielectrics of transistors
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申请号： US15595680申请日： 2017-05-15
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公开(公告)号： US10585643B2公开(公告)日： 2020-03-10
- 发明人: Xuefeng Gu , Subramanian S. Iyer
- 申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- 申请人地址： US CA Oakland
- 专利权人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- 当前专利权人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- 当前专利权人地址： US CA Oakland
- 代理机构： Foley & Lardner LLP
- 代理商 Cliff Z. Liu
- 主分类号： G06N3/063
- IPC分类号： G06N3/063 ; G11C11/54 ; G06F7/02 ; H01L29/792 ; G11C27/00 ; G11C16/04
摘要：
A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.
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