Invention Grant
- Patent Title: Method of signal integrity and power integrity analysis for address bus
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Application No.: US15991641Application Date: 2018-05-29
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Publication No.: US10585817B2Publication Date: 2020-03-10
- Inventor: Nitin Kumar Chhabra , Gaurav Mathur , Anant Dalimkar
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee Address: US CA Cupertino
- Agency: Westman, Champlin & Koehler, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F13/16 ; G01R31/27 ; G06F11/22

Abstract:
A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.
Public/Granted literature
- US20190370192A1 METHOD OF SIGNAL INTEGRITY AND POWER INTEGRITY ANALYSIS FOR ADDRESS BUS Public/Granted day:2019-12-05
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