公开(公告)号：US20250044343A1

公开(公告)日：2025-02-06

申请号：US18362744

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anil Dowleswarapu ,  Subramanian Narayan

IPC: G01R31/27 ,  G01R19/165

Abstract: An integrated circuit includes a current sense circuit having an input, an output, and a correction current input terminal between the input and output. A first transistor has a first control input and a first terminal. The first terminal is coupled to the input of the current sense circuit. A second transistor has a second control input and a second terminal. The second control input is coupled to the first control input, and the second terminal is coupled to the correction current input terminal.

公开(公告)号：US12209996B2

公开(公告)日：2025-01-28

申请号：US17430904

申请日：2020-01-28

Applicant: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY ,  HAMAMATSU PHOTONICS K.K.

Inventor： Naohiro Hozumi ,  Takuto Matsui ,  Toru Matsumoto ,  Shigeru Eura

IPC: G01N29/34 ,  G01N29/04 ,  G01N29/26 ,  G01N29/265 ,  G01N29/44 ,  G01R31/265 ,  G01R31/27 ,  G01R31/70

Abstract: An ultrasonic testing device having a packaged semiconductor device as a testing target, the device including: an ultrasonic oscillator disposed to face the semiconductor device; a pulse generator generating a driving signal that is used in the generation of an ultrasonic wave to be output from the ultrasonic oscillator; and an analysis unit analyzing an output signal that is output from the semiconductor device in accordance with the irradiation of the ultrasonic wave from the ultrasonic oscillator, in which the pulse generator sets an optimal frequency of the driving signal such that the absorption of the ultrasonic wave in the semiconductor device is maximized.

公开(公告)号：US12163995B2

公开(公告)日：2024-12-10

申请号：US18196380

申请日：2023-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ann Lai ,  Ruo-Rung Huang ,  Kun-Lung Chen ,  Chun-Yi Yang ,  Chan-Hong Chern

IPC: G01R31/26 ,  G01R31/27 ,  H03K3/017 ,  H03K17/687

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

公开(公告)号：US20240280627A1

公开(公告)日：2024-08-22

申请号：US18442731

申请日：2024-02-15

Applicant: ABB Schweiz AG

Inventor： Mikko Kohvakka ,  Kari Kovanen ,  Henri Hakkarainen

IPC: G01R31/26 ,  G01R31/27

CPC classification number: G01R31/2608 ,  G01R31/27

Abstract: The present invention relates to the field of electric drive devices and arrangements comprising a plurality of power semiconductor components formed in or on a common substrate, and more particularly to an arrangement for monitoring the condition of a power semiconductor module of an electric drive device and an electric drive device. The arrangement for monitoring the condition of a power semiconductor module of an electric drive device comprises at least one pair of sensor elements, each pair comprising a first PCB copper trace sensor element and a second PCB copper trace sensor element, arranged on a printed circuit board parallel next to each other as a sensor element pair, wherein said first PCB copper trace sensor element is connected to a positive DC supply voltage source (UDC+) and said second PCB copper trace sensor element is connected to a negative DC supply voltage source (UDC−) of said electric drive device so that upon applying the DC supply voltage of said electric drive device said DC supply voltage is applied to said at least one pair of sensor elements at the same time as to the circuit components of the power semiconductor module.

公开(公告)号：US12007429B2

公开(公告)日：2024-06-11

申请号：US17848972

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. Drennan ,  Joseph S. Spector ,  Richard Wunderlich

IPC: G01R31/27 ,  G01R1/073 ,  G01R31/26

CPC classification number: G01R31/275 ,  G01R1/07342 ,  G01R31/2601

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

公开(公告)号：US20240085967A1

公开(公告)日：2024-03-14

申请号：US18132394

申请日：2023-04-08

Applicant: SambaNova Systems, Inc.

Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/30 ,  G01R31/27 ,  G06F1/28 ,  G06F1/324

CPC classification number: G06F1/305 ,  G01R31/275 ,  G06F1/28 ,  G06F1/324

Abstract: An integrated circuit (IC) includes an array of compute units. Each compute unit is configured such that, when transitioning from not processing data to processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC. Control circuitry is configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from not processing data to processing data relative to when the other compute units start processing data to mitigate supply voltage overshoot caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.

公开(公告)号：US11881848B2

公开(公告)日：2024-01-23

申请号：US17435583

申请日：2020-02-27

Applicant: Webasto SE

Inventor： Philipp Eck

IPC: G01R31/26 ,  H03K17/18 ,  G01R31/27 ,  H03K17/082

CPC classification number: H03K17/18 ,  G01R31/2617 ,  G01R31/2621 ,  G01R31/275 ,  H03K17/082

Abstract: The invention provides a method for checking a semiconductor switch for a fault, wherein the semiconductor switch is driven with a PWM signal with a variable duty cycle. To the benefit of determining faults on the semiconductor switch reliably and cost-effectively, it is provided that if the semiconductor switch is operated with a duty cycle of 100% or 0%, the current measurement of the overall system is evaluated, while if the semiconductor switch is operated with a duty cycle of between 0% and 100%, the generated voltage pulses across the semiconductor switch are evaluated.

公开(公告)号：US11867722B1

公开(公告)日：2024-01-09

申请号：US18148318

申请日：2022-12-29

Applicant: Joseph Caba

Inventor： Joseph Caba

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  G01R31/27 ,  G01R31/52 ,  B63B79/30 ,  G01R31/00

CPC classification number: G01R1/06783 ,  B63B79/30 ,  G01R31/008 ,  G01R31/52

Abstract: Disclosed is a detector 10 using a liquid spray 2000 for detecting electrical faults or shorts with the detector including a body 100 having an interior 120; a hose or pipe 130 fluidly connected to interior 120; a trigger valve 140 operatively connected to hose 130; a conductor 200 attached to detector 10; and/or a pump 110 fluidly connected to interior 120. In various embodiments the detector 10 can cause liquid spray 2000 to be sprayed on a subregion of an item such as a remotely operated vehicle to create a closed electrical circuit through the liquid spray and the conductor in the detector.

公开(公告)号：US11721653B2

公开(公告)日：2023-08-08

申请号：US17125899

申请日：2020-12-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Javier A. DeLACruz ,  Belgacem Haba ,  Jung Ko

IPC: H01L23/00 ,  H01L25/065 ,  G01R31/28 ,  G01R31/27

CPC classification number: H01L24/06 ,  G01R31/275 ,  G01R31/2856 ,  H01L24/08 ,  H01L25/0657

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

公开(公告)号：US20230223361A1

公开(公告)日：2023-07-13

申请号：US18114123

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/498 ,  G01R31/27 ,  H01L23/522 ,  H01L23/544 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L23/585 ,  H01L22/32 ,  H01L23/49827 ,  G01R31/275 ,  H01L23/522 ,  H01L23/544 ,  H01L24/14 ,  H01L2924/1434 ,  H01L2224/32145 ,  H01L24/17 ,  H01L2223/54453 ,  H01L2224/1703 ,  H01L2224/81132 ,  H01L2924/1431 ,  H01L2924/3512 ,  H01L2223/54426 ,  H01L24/16 ,  H01L25/18 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/15192 ,  H01L2224/73267 ,  H01L24/92 ,  H01L2223/5442 ,  H01L2224/1403 ,  H01L2224/17153 ,  H01L2924/15313 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L25/0655 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L24/81 ,  H01L2924/15153 ,  H01L2224/81203 ,  H01L2224/171 ,  H01L2224/17177

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.