Invention Grant
- Patent Title: Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed
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Application No.: US15877931Application Date: 2018-01-23
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Publication No.: US10586738B2Publication Date: 2020-03-10
- Inventor: Wei-E Wang , Mark S. Rodder , Borna J. Obradovic , Joon Goo Hong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Van Pelt, Yi & James LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/08 ; H01L29/167 ; H01L21/225 ; H01L21/268 ; H01L21/324 ; H01L21/02 ; H01L29/78 ; H01L29/66
Abstract:
A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.
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