公开(公告)号：US20200066762A1

公开(公告)日：2020-02-27

申请号：US16666306

申请日：2019-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang Ill Seo ,  Borna J. Obradovic

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/477 ,  H01L27/088 ,  H01L21/027 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.

公开(公告)号：US10461751B2

公开(公告)日：2019-10-29

申请号：US16137227

申请日：2018-09-20

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Titash Rakshit

IPC: H01L27/115 ,  H03K19/0944 ,  H01L29/51 ,  G06N3/063 ,  H03K19/20 ,  H01L27/118

Abstract: A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

公开(公告)号：US20190181140A1

公开(公告)日：2019-06-13

申请号：US15977949

申请日：2018-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

公开(公告)号：US20180300618A1

公开(公告)日：2018-10-18

申请号：US15678050

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  H01L27/112 ,  G06N3/04

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US10026751B2

公开(公告)日：2018-07-17

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/01 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L29/10

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US20180130785A1

公开(公告)日：2018-05-10

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L23/532 ,  H01L29/47 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/665

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20180114727A1

公开(公告)日：2018-04-26

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US09741811B2

公开(公告)日：2017-08-22

申请号：US14961005

申请日：2015-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/775

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/78696

Abstract: Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.

公开(公告)号：US20160172358A1

公开(公告)日：2016-06-16

申请号：US14961005

申请日：2015-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic

IPC: H01L27/088 ,  H01L29/423

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/78696

Abstract: Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.

Abstract translation: 集成电路器件可以包括堆叠，其包括在垂直方向上以交替顺序堆叠的沟道区和栅电极。 沟道区可以包括具有第一导电类型的杂质。 集成电路器件还可以包括堆叠的相应相对侧上的源极/漏极区域，并且源极/漏极区域可以在水平方向上彼此间隔开，并且可以包括具有与第二导电类型不同的第二导电类型的杂质 第一导电类型。 集成电路器件还可以包括可以在相应的沟道区和源极/漏极区之一之间的延伸区域，并且可以包括具有第二导电类型的杂质。 每个延伸区域可以具有比沟道区域和源极/漏极区域中的一个小的垂直方向上的厚度。

公开(公告)号：US20160111337A1

公开(公告)日：2016-04-21

申请号：US14887484

申请日：2015-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

Abstract translation: 示例性实施例提供制造双轴应变纳米片。 示例性实施例的方面包括：生长具有一个或多个周期的外延晶体初始超晶格，每个周期包括至少三个层，活性材料层，第一牺牲材料层和第二牺牲材料层，第一和第二 具有不同材料特性的牺牲材料层; 在一个或多个周期的每一个中，将每个活性材料层放置在第一和第二牺牲材料层之间，其中第一和第二牺牲材料层的晶格常数不同于活性材料层并且在活性物质层中施加双轴应力 材料层; 选择性地蚀刻掉所有的第一牺牲材料层，从而暴露活性材料的一个表面以进行附加处理，同时活性材料层中的双轴应变由第二牺牲材料层保持; 并且选择性地蚀刻掉所有第二牺牲材料层，从而暴露活性材料层的第二表面用于额外的处理。