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    Integrated circuit devices including an element having a non-linear shaped upper surface and methods of forming the same
    1.
    发明授权
    Integrated circuit devices including an element having a non-linear shaped upper surface and methods of forming the same 有权

    公开(公告)号：US11581423B2

    公开(公告)日：2023-02-14

    申请号：US16947247

    申请日：2020-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang Ill Seo ,  Joon Goo Hong

    IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

    INTEGRATED CIRCUIT WITH BURIED POWER RAIL AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    INTEGRATED CIRCUIT WITH BURIED POWER RAIL AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220139835A1

    公开(公告)日：2022-05-05

    申请号：US17574073

    申请日：2022-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon Goo Hong ,  Kang-ill Seo ,  Mark S. Rodder

    IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06

    Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

    Low current leakage finFET and methods of making the same
    4.
    发明授权
    Low current leakage finFET and methods of making the same 有权

    公开(公告)号：US10930768B2

    公开(公告)日：2021-02-23

    申请号：US16282048

    申请日：2019-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Kang-ill Seo ,  Mark Stephen Rodder

    IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

    Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least a portion of the gate spacers to expose the extension portions of the fin, and thinning the extension portions of the fin. Following the thinning of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width less than the first width.

    POWER DISTRIBUTION NETWORK USING BURIED POWER RAIL
    5.
    发明申请
    POWER DISTRIBUTION NETWORK USING BURIED POWER RAIL 审中-公开

    公开(公告)号：US20200373241A1

    公开(公告)日：2020-11-26

    申请号：US16561340

    申请日：2019-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Michael Traynor

    IPC: H01L23/528 ,  H01L23/522

    Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 审中-公开

    公开(公告)号：US20200135735A1

    公开(公告)日：2020-04-30

    申请号：US16298887

    申请日：2019-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

    IPC: H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

    Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 审中-公开

    公开(公告)号：US20200135549A1

    公开(公告)日：2020-04-30

    申请号：US16283341

    申请日：2019-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

    IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

    Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

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