Invention Grant
- Patent Title: Three dimensional storage cell array with highly dense and scalable word line design approach
-
Application No.: US16045369Application Date: 2018-07-25
-
Publication No.: US10593624B2Publication Date: 2020-03-17
- Inventor: Deepak Thimmegowda , Aaron Yip , Mark Helm , Yongna Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L49/02 ; H01L23/522 ; H01L27/11524 ; H01L27/11578

Abstract:
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
Public/Granted literature
- US20180331034A1 THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH Public/Granted day:2018-11-15
Information query
IPC分类: