公开(公告)号：US10186325B2

公开(公告)日：2019-01-22

申请号：US15451777

申请日：2017-03-07

Applicant: Intel Corporation

Inventor： Mark Helm ,  Aaron Yip

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

公开(公告)号：US09620229B2

公开(公告)日：2017-04-11

申请号：US14926401

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Mark Helm ,  Jung Sheng Hoei ,  Aaron Yip ,  Dzung Nguyen

IPC: G11C16/04 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  H01L27/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/12 ,  G11C7/12 ,  G11C13/00 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C5/12 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C16/24 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  Y10T29/49155

Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.

公开(公告)号：US10593624B2

公开(公告)日：2020-03-17

申请号：US16045369

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Aaron Yip ,  Mark Helm ,  Yongna Li

IPC: H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

公开(公告)号：US10043751B2

公开(公告)日：2018-08-07

申请号：US15085151

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Aaron Yip ,  Mark Helm ,  Yongna Li

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11578

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

公开(公告)号：US20180261292A1

公开(公告)日：2018-09-13

申请号：US15451777

申请日：2017-03-07

Applicant: Intel Corporation

Inventor： Mark Helm ,  Aaron Yip

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G06F12/02 ,  G06F3/06

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

公开(公告)号：US09865357B1

公开(公告)日：2018-01-09

申请号：US15395700

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Pranav Kalavade ,  Aaron Yip ,  Shantanu R. Rajwade

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C5/063 ,  G11C5/145 ,  G11C8/00 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.