Invention Grant
- Patent Title: Vertical rectifier with added intermediate region
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Application No.: US16016510Application Date: 2018-06-22
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Publication No.: US10593813B2Publication Date: 2020-03-17
- Inventor: Richard A. Blanchard , Mohamed N. Darwish , Jun Zeng
- Applicant: MaxPower Semiconductor Inc.
- Applicant Address: US CA San Jose
- Assignee: MaxPower Semiconductor Inc.
- Current Assignee: MaxPower Semiconductor Inc.
- Current Assignee Address: US CA San Jose
- Agency: Groover & Associates PLLC
- Agent Robert O. Groover, III; Gwendolyn G. Corcoran
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/861 ; H01L29/40 ; H01L29/66 ; H01L21/265 ; H01L29/04 ; H01L29/16 ; H01L29/417

Abstract:
A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode. This advantageously permits the MOS channel portion to be reasonably short, and to have a reasonably low threshold voltage, since the high-voltage withstand characteristics are defined by the deep JFET-like device.
Public/Granted literature
- US20190067491A1 Vertical Rectifier with Added Intermediate Region Public/Granted day:2019-02-28
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