- 专利标题: Configuration of default voltage level for dual-voltage input/output pad cell via voltage rail ramp up timing
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申请号: US15269475申请日: 2016-09-19
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公开(公告)号: US10599197B2公开(公告)日: 2020-03-24
- 发明人: Haku Sato , Robert Greenwood , Paul M. Herbst
- 申请人: Freescale Semiconductor, Inc.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, INC.
- 当前专利权人: NXP USA, INC.
- 当前专利权人地址: US TX Austin
- 主分类号: G06F1/26
- IPC分类号: G06F1/26 ; G06F1/28 ; G06F9/4401 ; G11C5/14 ; G11C7/20 ; G11C16/20 ; G11C16/30
摘要:
An integrated circuit (IC) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The IC package further includes a set of one or more input/output (IO) pad cells and a power sequence detector coupled to the first and second voltage rails. The power sequence detector monitors the first and second voltage rails and configures the set of one or more IO pad cells to operate at one of a non-zero first voltage level or a non-zero second voltage level depending on which of the first voltage rail and the second voltage rail ramps up to a corresponding specified voltage level first.
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