Invention Grant
- Patent Title: Interconnect structures for preventing solder bridging, and associated systems and methods
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Application No.: US16182924Application Date: 2018-11-07
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Publication No.: US10600750B2Publication Date: 2020-03-24
- Inventor: Kyle S. Mayer , Owen R. Fay
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/288

Abstract:
Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.
Public/Granted literature
- US20190198470A1 INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS Public/Granted day:2019-06-27
Information query
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