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    SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES
    4.
    发明公开
    SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES 审中-公开

    公开(公告)号：US20230317511A1

    公开(公告)日：2023-10-05

    申请号：US18111496

    申请日：2023-02-17

    申请人： Micron Technology, Inc.

    发明人： Andrew M. Bayless ,  Brandon P. Wirz ,  Owen R. Fay

    IPC分类号： H01L21/768 ,  H01L21/02 ,  G03F7/004 ,  G03F7/20

    CPC分类号： H01L21/76801 ,  G03F7/004 ,  G03F7/20 ,  H01L21/02348

    摘要： A method for smoothing structures formed of curable materials on a semiconductor device includes applying a layer of photo-responsive material on a substrate. The photo-responsive material is exposed to ultraviolet light through a grayscale gradient mask. Subsequent to removing unwanted portions of the photo-responsive material, the photo-responsive material that remains on the substrate is cured. During the curing process, the temperature is increased from a starting temperature to a final cure temperature over a first time period that allows the photo-responsive material to cross-flow. The temperature of the photo-responsive material is maintained at approximately the final cure temperature for a second time period, and then the temperature of the photo-responsive material is decreased to a predetermined finish temperature over a third time period.

    High density pillar interconnect conversion with stack to substrate connection
    5.
    发明授权
    High density pillar interconnect conversion with stack to substrate connection 有权

    公开(公告)号：US11631644B2

    公开(公告)日：2023-04-18

    申请号：US17221537

    申请日：2021-04-02

    申请人： Micron Technology, Inc.

    发明人： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

    摘要： A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

    Tunable integrated millimeter wave antenna using laser ablation and/or fuses
    6.
    发明授权
    Tunable integrated millimeter wave antenna using laser ablation and/or fuses 有权

    公开(公告)号：US11588233B2

    公开(公告)日：2023-02-21

    申请号：US16045562

    申请日：2018-07-25

    申请人： Micron Technology, Inc.

    发明人： John F. Kaeding ,  Owen R. Fay

    IPC分类号： H01Q1/48

    摘要： A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.

    High density pillar interconnect conversion with stack to substrate connection
    7.
    发明授权
    High density pillar interconnect conversion with stack to substrate connection 有权

    公开(公告)号：US11587912B2

    公开(公告)日：2023-02-21

    申请号：US17383304

    申请日：2021-07-22

    申请人： Micron Technology, Inc.

    发明人： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/60

    摘要： A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

    Semiconductor assemblies with redistribution structures for die stack signal routing
    8.
    发明授权
    Semiconductor assemblies with redistribution structures for die stack signal routing 有权

    公开(公告)号：US11552045B2

    公开(公告)日：2023-01-10

    申请号：US17100610

    申请日：2020-11-20

    申请人： Micron Technology, Inc.

    发明人： Owen R. Fay ,  Madison E. Wale ,  James L. Voelz ,  Dylan W. Southern ,  Dustin L. Holloway

    IPC分类号： H01L23/00

    摘要： Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.

    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220293506A1

    公开(公告)日：2022-09-15

    申请号：US17830022

    申请日：2022-06-01

    申请人： Micron Technology, Inc.

    发明人： Owen R. Fay ,  Jack E. Murray

    IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    摘要： Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same
    10.
    发明授权
    Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US11309285B2

    公开(公告)日：2022-04-19

    申请号：US16440328

    申请日：2019-06-13

    申请人： Micron Technology, Inc.

    发明人： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

    IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

    摘要： Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.