Invention Grant
- Patent Title: Twin bit non-volatile memory cells with floating gates in substrate trenches
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Application No.: US16160812Application Date: 2018-10-15
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Publication No.: US10600794B2Publication Date: 2020-03-24
- Inventor: Chunming Wang , Andy Liu , Xian Liu , Leo Xing , Melvin Diao , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Priority: CN201810011007 20180105
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/788 ; H01L29/423 ; H01L27/11521 ; H01L27/11524 ; H01L21/28

Abstract:
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
Public/Granted literature
- US20190214396A1 Twin Bit Non-volatile Memory Cells With Floating Gates In Substrate Trenches Public/Granted day:2019-07-11
Information query
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