- 专利标题: Self-clocking sampler with reduced metastability
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申请号: US15693325申请日: 2017-08-31
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公开(公告)号: US10601409B2公开(公告)日: 2020-03-24
- 发明人: John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
- 申请人: NVIDIA Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: NVIDIA Corporation
- 当前专利权人: NVIDIA Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Leydig, Voit & Mayer, Ltd.
- 主分类号: H03K3/356
- IPC分类号: H03K3/356 ; H03K5/135 ; H03K19/096 ; H02M3/156 ; G05F1/575
摘要:
A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
公开/授权文献
- US20190068203A1 SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY 公开/授权日:2019-02-28
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