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公开(公告)号：US20230145487A1
公开(公告)日：2023-05-11
申请号：US17523358
申请日：2021-11-10
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , John Michael Wilson
IPC: G05F1/46
Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.
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公开(公告)号：US20180191349A1
公开(公告)日：2018-07-05
申请号：US15908242
申请日：2018-02-28
Applicant: NVIDIA Corporation
Inventor： John Michael Wilson , John W. Poulton , Matthew Rudolph Fojtik , Carl Thomas Gray
IPC: H03K19/0185
CPC classification number: H03K19/018528
Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
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公开(公告)号：US11829170B2
公开(公告)日：2023-11-28
申请号：US17523358
申请日：2021-11-10
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , John Michael Wilson
IPC: G05F1/46
Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.
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公开(公告)号：US20170093403A1
公开(公告)日：2017-03-30
申请号：US14869759
申请日：2015-09-29
Applicant: NVIDIA Corporation
Inventor： John Michael Wilson , John W. Poulton , Matthew Rudolph Fojtik , Carl Thomas Gray
IPC: H03K19/0185
CPC classification number: H03K19/018528
Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
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Patent Agency Ranking
公开(公告)号：US10601409B2
公开(公告)日：2020-03-24
申请号：US15693325
申请日：2017-08-31
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
IPC: H03K3/356 , H03K5/135 , H03K19/096 , H02M3/156 , G05F1/575
Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
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公开(公告)号：US10164638B2
公开(公告)日：2018-12-25
申请号：US15908242
申请日：2018-02-28
Applicant: NVIDIA Corporation
Inventor： John Michael Wilson , John W. Poulton , Matthew Rudolph Fojtik , Carl Thomas Gray
IPC: H03K19/0175 , H03K19/0185
Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
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公开(公告)号：US09954527B2
公开(公告)日：2018-04-24
申请号：US14869759
申请日：2015-09-29
Applicant: NVIDIA Corporation
Inventor： John Michael Wilson , John W. Poulton , Matthew Rudolph Fojtik , Carl Thomas Gray
IPC: H03K19/0175 , H03K19/0185
CPC classification number: H03K19/018528
Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
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公开(公告)号：US10298422B1
公开(公告)日：2019-05-21
申请号：US15862517
申请日：2018-01-04
Applicant: NVIDIA Corporation
Inventor： Sanquan Song , Nikola Nedovic , John Michael Wilson , John W. Poulton , Walker Joseph Turner
Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.
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公开(公告)号：US20190068203A1
公开(公告)日：2019-02-28
申请号：US15693325
申请日：2017-08-31
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
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