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    Self-clocking sampler with reduced metastability
    1.
    发明授权
    Self-clocking sampler with reduced metastability 有权

    公开(公告)号：US10601409B2

    公开(公告)日：2020-03-24

    申请号：US15693325

    申请日：2017-08-31

    Applicant: NVIDIA Corporation

    Inventor： John W. Poulton ,  Sudhir Shrikantha Kudva ,  Stephen G. Tell ,  John Michael Wilson

    IPC: H03K3/356 ,  H03K5/135 ,  H03K19/096 ,  H02M3/156 ,  G05F1/575

    Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

    LOW-POWER DYNAMIC OFFSET CALIBRATION OF AN ERROR AMPLIFIER
    3.
    发明公开
    LOW-POWER DYNAMIC OFFSET CALIBRATION OF AN ERROR AMPLIFIER 审中-公开

    公开(公告)号：US20230145487A1

    公开(公告)日：2023-05-11

    申请号：US17523358

    申请日：2021-11-10

    Applicant: NVIDIA Corporation

    Inventor： John W. Poulton ,  Sudhir Shrikantha Kudva ,  John Michael Wilson

    IPC: G05F1/46

    CPC classification number: G05F1/461 ,  G05F1/468

    Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

    Low-power dynamic offset calibration of an error amplifier
    4.
    发明授权
    Low-power dynamic offset calibration of an error amplifier 有权

    公开(公告)号：US11829170B2

    公开(公告)日：2023-11-28

    申请号：US17523358

    申请日：2021-11-10

    Applicant: NVIDIA Corporation

    Inventor： John W. Poulton ,  Sudhir Shrikantha Kudva ,  John Michael Wilson

    IPC: G05F1/46

    CPC classification number: G05F1/461 ,  G05F1/468

    Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

    MAGNETIC POWER COUPLING TO AN INTEGRATED CIRCUIT MODULE
    5.
    发明申请
    MAGNETIC POWER COUPLING TO AN INTEGRATED CIRCUIT MODULE 审中-公开
    磁电耦合到集成电路模块

    公开(公告)号：US20160043569A1

    公开(公告)日：2016-02-11

    申请号：US14815853

    申请日：2015-07-31

    Applicant: NVIDIA Corporation

    Inventor： William J. Dally ,  Thomas Hastings Greer, III ,  Sudhir Shrikantha Kudva

    IPC: H02J5/00 ,  H01F27/28 ,  H01F27/24

    CPC classification number: H01F27/027 ,  H01F27/24 ,  H01F27/2823 ,  H01F38/14 ,  H02J5/00 ,  H02J5/005 ,  H02J50/10

    Abstract: A magnetic power supply coupling system is disclosed. An integrated circuit module includes an integrated circuit die and a secondary winding that is configured to generate an induced, alternating current based on a magnetic flux. A primary winding is external to the integrated circuit module, proximate to the integrated circuit module, and coupled to a main power supply corresponding to an alternating current that generates the magnetic flux. The induced, alternating current is converted into a direct current at a voltage level to supply power to the integrated circuit die.

    Abstract translation: 公开了一种磁电源耦合系统。 集成电路模块包括集成电路管芯和次级绕组，其被配置为基于磁通量产生感应的交流电流。 初级绕组在集成电路模块的外部，靠近集成电路模块，并且耦合到对应于产生磁通量的交流电的主电源。 感应的交流电被转换成电压电平的直流电，以向集成电路管芯供电。

    SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY
    8.
    发明申请
    SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY 审中-公开

    公开(公告)号：US20190068203A1

    公开(公告)日：2019-02-28

    申请号：US15693325

    申请日：2017-08-31

    Applicant: NVIDIA Corporation

    Inventor： John W. Poulton ,  Sudhir Shrikantha Kudva ,  Stephen G. Tell ,  John Michael Wilson

    IPC: H03L7/087 ,  H03K5/135 ,  G06F17/50 ,  G11C7/10 ,  H03K3/356

    Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

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