Invention Grant
- Patent Title: Method of reducing power dissipation in a clock distribution network for integrated circuit
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Application No.: US16263705Application Date: 2019-01-31
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Publication No.: US10606306B2Publication Date: 2020-03-31
- Inventor: Tomas Alexander Dusatko
- Applicant: INPHI CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: G06F1/10
- IPC: G06F1/10 ; H01F17/00 ; H03H7/01 ; G06F1/32 ; H03H11/28 ; H01L23/66 ; H03H7/09 ; H03H7/38

Abstract:
A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.
Public/Granted literature
- US20190163230A1 METHOD OF REDUCING POWER DISSIPATION IN A CLOCK DISTRIBUTION NETWORK FOR INTEGRATED CIRCUIT Public/Granted day:2019-05-30
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